1. Field of the Invention
This invention relates to a random access memory device and, more particularly, is directed to a method of fabricating a dynamic random access memory (DRAM) cell having a fin-type stacked capacitor with increased capacitance.
2. Description of the Prior Art
The integrated circuit density on the semiconductor substrate and the semiconductor chips formed therefrom, has dramatically increased in recent years. This increase in density has resulted from down scaling of the individual devices built in and on the substrate and the increase in packing density. Future requirements for even greater increases in packing density is putting additional demand on the semiconductor technologies and more particularly on the photolithographic techniques.
One circuit type experiencing this demand for increased density is the array of charge storage cells on a dynamic random access memory (DRAM) chip. These individual DRAM storage cells, consisting usually of a field-effect transistor (FET) and a single capacitor are used extensively in the electronics industry for storing data. A single DRAM storage cell stores a bit of data on the capacitor as electrical charge.
As the array of cells increase on the DRAM chip and capacitor decrease in size, it becomes increasingly difficult to maintain sufficient charge on the storage capacitor to maintain an acceptable signal-to-noise level. These volatile storage cells also require more frequent refresh cycles in order to retain their charge.
Since the storage capacitor must occupy an area limited by the cell size, in order to accommodate the array of capacitors on the chip, it is necessary to explore alternative methods for increasing the capacitance without increasing the area that the capacitor occupies on the substrate surface.
Both a trench capacitor, formed in the substrate, and a stacked capacitor, formed on the surface and over the FET, are currently being pursued for DRAM applications. Several approaches to making DRAM circuits using trench capacitors have been described in U.S. Pat. No. 4,914,628 by T. Nishimura, in U.S. Pat. No. 5,164,917 by H. Shichijo and by R. D. Sivan in U.S. Pat. No. 5,244,824. However, the stacked capacitors has received considerable interest in recent years because of the variety of ways that its shape can be controlled to increase the capacitance without increasing the area it occupies on the substrate. This makes the stacked capacitor very desirable for DRAM application.
Numerous three-dimensional stacked capacitor structures have been reported. For example, H--H. Tseng, U.S. Pat. No. 5,192,702 teaches methods of fabricating vertical sidewall capacitors and P. Fazan et al, U.S. Pat. No. 5,084,405 teaches methods of forming double ring stacked capacitors structures using sidewall spacer techniques.
However, one type of three-dimensional stacked capacitor structure receiving considerable interest is the capacitor having a fin shaped electrodes extending up-ward and over the cell area. For example, H. Ogawa et al describes a method in U.S. Pat. No. 5,164,337, in which a multilayer of dissimilar insulators or a multilayer of dissimilar doped polysilicon layers are patterned over the insulated substrate to form a fin-type capacitor.
Most of these stacked fin-type capacitor structures require additional processing steps and the underlying device structures must also be protected from process damage when the stacked storage capacitor is being fabricated on the substrate.
Although there has been considerable work done to increase the capacitance area on these very small stacked fin shaped capacitors, it is still desirable to further improve these capacitors while retaining as simple a process as possible to maintain high chip yields, low cost and good reliability. This is especially true as the DRAM increase to 64 Mbits on a chip.